FIELD OF THE INVENTION
The invention relates to a method for fabricating an integrated circuit configuration.
Endeavors are generally made to produce an integrated circuit configuration with an ever higher packing density.
A reference by Y. Hayashi et al., titled "Fabrication of Three-Dimensional IC Using Cumulatively Bonded IC (CUBIC) Technology", IEEE Symposium on VLSI Technology (1990), 95, describes a method for fabricating a three-dimensional integrated circuit configuration in which substrates containing semiconductor components are stacked one above the other. First, the semiconductor components are produced in the substrates. Each substrate is provided with a metalization plane that connects the semiconductor components of the substrate to one another. Tungsten pins are applied on each metalization plane. A first of the substrates is applied to a support substrate in such a way that its front side, on which the tungsten pins are disposed, adjoins the support substrate. A rear side of the first substrate is then thinned by grinding and provided with a further metalization plane. Depressions are produced in the rear side of the first substrate and their surfaces are provided with an Au--In alloy. A polymide layer is subsequently applied on the rear side of the first substrate. A second of the substrates is subsequently connected to the first substrate in such a way that the tungsten pins of the second substrate descend into the depressions on the rear side of the first substrate. The second substrate is aligned with respect to the first substrate with the aid of an infrared microscope. In order to connect the first substrate to the second substrate, the temperature is initially increased until the Au--In alloy melts. The temperature is then reduced to room temperature. The two substrates are pressed one on top of the other in the process. The support material is subsequently removed. The tungsten pins serve as contacts between the semiconductor components of the first substrate and the semiconductor components of the second substrate. The three-dimensional integration of substrates allows the integrated circuit configuration to have a particularly high packing density.